1. Field of the Invention
Generally, the subject matter disclosed herein relates to integrated circuits, and, more particularly, to contact features for connecting contact areas or metal regions of semiconductor devices with conductive lines or regions, such as metal lines, in a higher wiring level of the semiconductor device.
2. Description of the Related Art
The fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in one or more material layers of an appropriate substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate or other suitable carrier materials. These tiny regions of precisely controlled size are typically defined by patterning the material layer(s) by applying lithography, etch, implantation, deposition processes and the like, wherein, typically, at least in a certain stage of the patterning process, a mask layer may be formed over the material layer(s) to be treated to define these tiny regions. Generally, a mask layer may consist of or may be formed by means of a layer of photoresist that is patterned by a lithographic process, typically a photolithography process. During the photolithography process, the resist may be spin-coated onto the substrate surface and then selectively exposed to ultraviolet radiation through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into the resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Based on this resist pattern, actual device patterns may be formed by further manufacturing processes, such as etch, implantation, anneal processes and the like. Since the dimensions of the patterns in sophisticated integrated microstructure devices are steadily decreasing, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is considered as a measure for specifying the consistent ability to print minimum size images under conditions of predefined manufacturing variations. One important factor in improving the resolution is the lithographic process, in which patterns contained in the photo mask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used.
The resolution of the optical patterning process may, therefore, significantly depend on the imaging capability of the equipment used, the photoresist materials for the specified exposure wavelength and the target critical dimensions of the device features to be formed in the device level under consideration. For example, gate electrodes of field effect transistors, which represent an important component of modern logic devices, may have a length of 50 nm and less for currently produced devices, with significantly reduced dimensions for device generations that are currently under development. Similarly, the line width of metal lines provided in the plurality of wiring levels or metallization layers may also have to be adapted to the reduced feature sizes in the device layer in order to account for the increased packing density. Consequently, the actual feature dimensions may be well below the wavelength of currently used light sources provided in current lithography systems. For example, currently in critical lithography steps, an exposure wavelength of 193 nm may be used, which, therefore, may require complex techniques for finally obtaining resist features having dimensions well below the exposure wavelength. Thus, highly non-linear processes are typically used to obtain dimensions below the optical resolution. For example, extremely non-linear photo-resist materials may be used, in which a desired photochemical reaction may be initiated on the basis of a well-defined threshold so that weakly exposed areas may not substantially change at all, while areas having exceeded the threshold may exhibit a significant variation of their chemical stability with respect to a subsequent development process.
In particular, during the patterning of dielectric materials of metal systems of sophisticated semiconductor devices, precisely defined etch masks may be required in order to provide an appropriate template for etching through a moderately thick dielectric material, which may thus impose significant restrictions on the corresponding etch strategy. Consequently, any irregularities occurring during the complex lithography process may translate into even further increased irregularities after completing the complex etch process. Due to the complex interaction between the imaging system used during the lithography process, the resist material and the corresponding pattern provided on the lithography mask or reticle, typically, highly sophisticated imaging techniques, including optical proximity corrections (OPC), may be applied. In OPC strategies, very complex calculations are applied in order to predict the characteristics of latent images and resist features after imaging the pattern of the lithography mask into the photoresist layer. For this purpose, the specific conditions of the lithography process, such as exposure wavelength, resist material, critical dimensions of the circuit features and the like, may be entered into an appropriate model, which in turn may provide “modified” layouts for the individual circuit features, such as lines and the like, in order to avoid or at least reduce any undesired distortions of circuit features upon imaging the pattern from the photolithography mask into the resist material. Such OPC models may involve a plurality of parameters, wherein efficiency of the OPC model under consideration strongly depends on the range of many input parameters. That is, efficient OPC models may require a more or less restricted range of parameters, such as critical dimensions of circuit features for otherwise identical conditions. Consequently, when imaging circuit features, such as contact openings or via openings, into a resist material, wherein a significant difference in lateral dimensions is required, the OPC model may be less efficient and may thus result in lithography-related irregularities.
Furthermore, during the complex patterning process for forming metallization systems of semiconductor devices, frequently, a process strategy may be applied in which via openings and trenches may be formed in a patterning sequence and these openings may be filled in a common deposition process in order to enhance overall process efficiency. Since the via openings and the trenches may extend to a different depth in the dielectric material, i.e., the via openings may provide connection to a lower-lying metallization level, a patterning sequence is required in which different lithography processes may have to be performed on the basis of a pronounced surface topography, which may also contribute to further process irregularities, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 which comprises a substrate 101 above which are formed various levels, such as a level including semiconductor elements and the like, in combination with a metallization system 150. For convenience, circuit elements such as transistors, resistors and the like are not shown in FIG. 1a. In the example shown, the metallization system 150 comprises a first metallization layer 110 including an appropriate dielectric material 111 in combination with metal regions 112A, 112B. Furthermore, a cap layer or etch stop layer 113 is formed above the dielectric material 111 and the metal regions 112A, 112B. The dielectric material 111 may represent any appropriate material, such as silicon dioxide, low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of 3.0 or less, and the like. Similarly, the metal regions 112A, 112B may comprise any appropriate conductive material, such as copper, in combination with conductive barrier materials and the like. Similarly, the etch stop layer 113 may typically be comprised of a silicon nitride-based material, such as a carbon-containing silicon nitride and the like. As previously explained, lateral dimensions of the metal regions 112A, 112B may be approximately 100 nm and less for critical circuit features, while, in the same device level, metal regions of significantly greater dimensions may also have to be provided. For instance, it may be assumed that the lateral dimensions of the metal region 112B may be at least twice the lateral dimensions of the metal region 112A.
Moreover, the metallization system 150 comprises a second metallization layer 120 which, in the manufacturing stage shown, comprises an appropriate dielectric material 121, such as a low-k dielectric material and the like. Furthermore, an etch mask 102 is formed above the dielectric material 121 and may comprise openings 102A, 102B which determine the lateral position and size of via openings to be formed in the dielectric material 121 so as to connect to the metal regions 112A, 112B. In the example shown, the mask openings 102A, 102B may be adapted to the size of the metal regions 112A, 112B, at least in one lateral direction, i.e., in FIG. 1a, in the horizontal direction, thereby also requiring the openings 102A, 102B to have significantly different lateral dimensions, as indicated by 103A, 103B.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of any appropriate process strategy for providing semiconductor-based circuit elements in one or more semiconductor layers, followed by process techniques for forming the metallization system 150. For convenience, a corresponding process strategy will be explained with reference to the metallization layer 120, wherein it should be appreciated that similar process techniques may also be applied for forming the metallization layer 110. Thus, the dielectric material 121 may be formed on the cap layer or etch stop layer 113, which may be accomplished by any appropriate deposition technique such as chemical vapor deposition (CVD), spin-on techniques and the like. Thereafter, appropriate materials, such as anti-reflective coating (ARC) materials, hard mask materials and the like, may be deposited and may be used for the subsequent complex lithography process. As previously explained, during a lithography process, a desired pattern may be provided in a lithography mask and may be imaged into a resist layer (not shown) so as to form a latent image therein, wherein the characteristics of the imaging process may strongly depend on the type of resist material used, the exposure wavelength, the characteristics of the lithography equipment, for instance in terms of numerical aperture, depth of focus, and the like. Furthermore, as discussed above, the finally obtained result of the lithography process may also depend on the efficiency of optical proximity correction mechanisms that are based on appropriately selected input parameters and thus OPC models. For instance, if the lateral dimension 103A is to be considered as a critical dimension for the lithography process under consideration, corresponding OPC mechanisms may be triggered such that, preferably, the opening 102A with the critical dimension 103A may be obtained with a high degree of precision, thereby possibly negatively affecting the quality of the imaging process with respect to the opening 102B.
Based on a corresponding resist material, the etch mask 102 may be patterned and/or the resist material may also be used, possibly in combination with the additional materials, as the etch mask 102. Subsequently, a plasma assisted etch process is performed in which an appropriate etch chemistry is applied so as to etch through the semiconductor material 121, while a corresponding etch rate in the etch mask 102 is significantly less. For this purpose, a plurality of well-established etch recipes are available, wherein, however, the etch fidelity may depend on the quality of the etch mask 102 and any process variations during the sophisticated etch process. For instance, the local etch conditions, such as the presence of reactive components, polymer additives and the like, may vary, depending on the packing density of features and the size thereof. For example, due to the increased lateral dimension 103B, the local etch rate may be different in this area compared to the area corresponding to the opening 102A.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which via openings 121A and 121B are formed in the dielectric material 121 and the etch mask 102 (FIG. 1a) is removed. As illustrated, the openings 121A, 121B extend to the etch stop layer 113, wherein, depending on the local variation of the etch conditions, a more or less degree of material erosion may occur in the opening 121A, 121B.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, an optical planarization layer (OPL) 103 is formed above the dielectric material 121 and within the openings 121A, 121B. The optical planarization material 103 is typically provided as an organic material that may be applied on the basis of spin-on techniques in a low viscous state, wherein superior gap fill capabilities of this material may result in the filling of the openings 121A, 121B, while also an additional material layer is formed above the dielectric material 121, which may thus be used as an ARC material, etch mask material and the like. Upon the continuous reduction of the overall feature sizes, however, the lateral dimensions of the via openings have reached values of 100 nm and even less so that the reliable filling of critical openings, such as the opening 121A, may become increasingly difficult. At the same time, the fill behavior in significantly greater openings, such as the opening 121B, may strongly differ to that of the critical opening 121A, thereby resulting in a pronounced surface topography of the layer 103 so that the “planarizing effect” of the material 103 may be significantly restricted by the presence of openings of very different lateral dimensions. Consequently, in a subsequent lithography process in which a further etch mask 104, such as a resist mask, is to be provided with corresponding openings 104A, 104B defining the lateral size and position of corresponding trenches, even further sophisticated conditions may be encountered. That is, due to the pronounced surface topography, corresponding variations of the exposure process may occur, for instance, due to the very restricted depth of focus and the like. Furthermore, during the subsequent etch process for patterning the planarization material 103 and etching into the dielectric material 121 so as to form corresponding trenches 121C, 121D therein, further process irregularities may occur due to imperfections of the etch mask 104 caused by lithography irregularities and due to etch variations caused by the pronounced surface topography.
Consequently, upon the further processing, i.e., the filling of trenches 121C, 121D and the via openings 121A, 121B with a conductive material, such as copper and the like, significant variations of the resulting metal features may be observed which may, however, contribute to significantly increased yield losses.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.